Ferroelectric compute-in-memory and the MEA forecasting edge

What the work claims

Katti, Selvakumar, Chaudhari and Jariwala introduce FerroNDS, a neuromorphic architecture built from two analog primitives: an integrator for temporal accumulation and an oscillator for frequency-selective filtering.¹ The synaptic weights are stored in multi-bit ferroelectric diodes (FeDs), giving the system a compute-in-memory back-end. A 128-neuron instance computes a short-time Fourier transform and forecasts a 500 ms horizon for periodic, quasi-periodic and chaotic signals with a reported mean-squared error of 0.32 or below.

The paper reports simulated energy and latency numbers derived from LTspice circuit simulations. At 200 Hz operation, per-neuron per-inference energy is 1.64 µJ; at 10 kHz it is 0.29 µJ. The system is projected to be 25 to 40 times smaller in memory-cell area than an SRAM-based digital implementation, with FeD write energy below 10 fJ per bit. Worst-case per-layer latency is 3.18 ms at 200 Hz and 63.87 µs at 10 kHz. The authors state this is the first end-to-end integration of a ferrodiode into a neuromorphic computational framework.

How it works

Neural dynamical systems advance a latent state in small time steps, a pattern that maps poorly onto digital hardware built for dense matrix operations. FerroNDS instead realizes the differential equations directly in analog circuits. The integrator implements a leaky integrator, and the oscillator implements a damped harmonic oscillator, or bandpass resonator, with a resonant frequency set by an LC-tank network. Together they form a continuous-time state-space model that can be trained to predict future samples from past ones.

The FeD is the memory element. The device used in the paper is a 20 nm aluminum scandium nitride film with a 5 nm aluminum oxide interlayer, reported by the same research group's collaborators to show 32 conductance states and an on/off ratio of 1,175. The FeD's current-voltage relation is exponential, so the authors wrap it in a five-stage synaptic circuit: a scale/bias stage, a transimpedance amplifier, a sense amplifier with gain of 1,000, a logarithmic amplifier to undo the exponential non-linearity, and a final scale/bias stage. A state-selection algorithm picks eight states from the 32 available that satisfy minimum current, exponential-fit quality, linear spacing of coefficients and uniformity constraints, all within a 6.45 to 7.45 V operating window.

The system is trained in Python with PyTorch using discrete versions of the integrator and oscillator, then mapped back to the analog parameters. Circuit simulations use macromodels of the Analog Devices LT6003 op-amp for the 200 Hz setting and the LTC2068 for the 10 kHz setting. Energy estimates combine the op-amp quiescent currents with the number of high-voltage and low-voltage op-amps in each synaptic path.

Where a skeptic should push

The central caveat is that FerroNDS is a simulation study, not a fabricated chip. The FeD current-voltage data come from a prior device paper and are used as a macromodel in LTspice. The integrator, oscillator and synaptic circuits have not been taped out, so none of the headline energy or latency numbers have been measured from silicon. Device-to-device variation, noise, temperature drift and crosstalk in a dense analog array are all present in the real world but absent from the simulation.

The workload is also narrow. The 500 ms horizon prediction is demonstrated on synthetic one-dimensional signals sampled at 1 kHz: noisy sine and square waves, amplitude-modulated sines, chirps, envelope-modulated sines, a composite waveform and a Mackey-Glass chaotic series. These are useful benchmarks, but they are not extracellular neural recordings. MEA data are multichannel, non-stationary and buried in noise, and a model that works on clean synthetic chirps may not transfer without significant redesign.

The operating voltage is another concern. The selected FeD states sit between 6.45 and 7.45 V, far above the low-voltage CMOS that dominates MEA readouts. The authors note that ferrodiodes have been demonstrated down to 2 V and that such a reduction would cut synaptic circuit energy by 4.5 times at 200 Hz and 20 times at 10 kHz, but that projection is not what the reported numbers are based on. Finally, the resonant oscillator is designed for 200 Hz; higher frequencies require faster op-amps and higher power, which would limit use for high-gamma or fast-spike features unless the architecture is scaled.

What it means for analog MEA back-end forecasting

The non-obvious opportunity is to move inference onto the array itself. Today the MEA acquisition chain is dominated by analog front-end amplification, multiplexing, analog-to-digital conversion and high-speed data egress. FerroNDS suggests a different division of labor: let the analog front end not only amplify and sample but also predict the near future of each channel using a compact continuous-time model. If the predictor is good enough, the system can transmit only residuals or event flags rather than full waveforms, cutting the egress bandwidth and the storage burden.

The second opportunity is online adaptation. Ferroelectric diodes are non-volatile and, according to the paper, can be written with below 10 fJ per bit. A write energy that low makes in-situ weight updates plausible, which matters for arrays that need to track drifting organoid activity without shipping every sample to a host computer. An analog back-end that slowly learns the statistical structure of a culture's bursts could, in principle, tune its own detection thresholds or forecast models while the experiment runs.

The genuine threat is the simulation-to-reality gap. Organoid recordings contain movement artifacts, temperature drift, evaporation-induced impedance changes and slow baseline wander. These effects are hard to model in LTspice. A 128-neuron network is also tiny compared with modern deep-learning decoders, and the 500 ms horizon that looks good on synthetic signals may be unreliable on real data. There is also a thermal and packaging question: if the analog compute array is integrated with the MEA substrate inside an incubator, self-heating from the op-amps and FeD peripheral circuits could affect the culture.

From an instrumentation standpoint, the most useful near-term contribution may be the benchmarking framework itself. The paper reports energy per neuron per inference, area per memory cell, write energy and latency in a single coherent table, using plausible device models and circuit schematics. That gives MEA hardware designers a reference point for what an on-array predictor would need to beat. For now, FerroNDS is a design target, not a drop-in back-end, and any organoid application would need to prove it on real spikes before it changes how arrays are built.

The bottom line

FerroNDS is a careful device-circuit-algorithm co-design that combines multi-bit ferroelectric memory with analog neural dynamical systems. Its headline numbers - sub-watt operation, microjoule-per-inference energy and 25 to 40 times area reduction over SRAM - are attractive, but they are all derived from simulation. For microelectrode arrays, the paper's real value is conceptual: it lays out a plausible path toward on-array, continuous-time forecasting. The next step that would matter is a small silicon demonstration on actual neural or organoid data, with measured variation and noise included.