Analog memory that forgets, and what it costs an at-array processor
A group at Pisa fabricated a floating-gate analog compute array in a standard 65 nm process, let it sit for two months, and measured how much its stored weights drifted. Their fix restores accuracy to within a few points, but it takes two independent corrections working together. The real question for putting analog computation at the electrode is not whether that compensation loop can run, but what a warm, living, drifting environment does to it.
Source: Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing, arXiv (cs.AR), 27 July 2026. Primary source. Read the full PDF, including the device, retention and mitigation results.
What the work claims
The paper is a device-to-system reliability study of analog in-memory computing, the scheme where a neural network's weights are stored as physical charge in a memory array and multiplication happens in place, avoiding the energy cost of shuttling data to a separate processor.1 The medium here is a single-poly floating-gate cell in a TSMC 65 nm CMOS process, one weight-storing transistor in series with a selector, at a footprint of 0.88 by 0.64 micrometres. Each cell behaves as a programmable current source tunable over more than two decades, from roughly 0.4 to 80 nanoamps, operating in the subthreshold regime near a 1 volt read bias.
The central claim is quantitative: floating-gate charge leaks away over weeks, corrupting the stored weights, but the damage can be largely undone. Using a model of retention statistics calibrated against measured silicon at 10, 30 and 60 days, and running it through image-classification networks, the authors show that combining an adaptive read voltage with a statistical recalibration step recovers baseline accuracy to within about 2 to 4 percent after 60 days. This is a measured-and-simulated hybrid: the retention behaviour is real device data, while the accuracy numbers come from Monte Carlo simulation, five hundred runs, on that calibrated model, not from a fabricated end-to-end accelerator.
How the drift happens and how they undo it
Charge stored on a floating gate slowly leaks. As it does, the transistor's threshold voltage falls and the current it sources at a fixed read voltage rises, so a weight programmed to one value silently reads back as another. In a digital memory this would be a bit error, correctable by codes; in an analog memory each cell's current directly is the weight, so leakage perturbs the computation itself with no clean error-correction fallback. The authors measured this by programming cells across the 0.4 to 80 nanoamp range and re-reading them after 10, 30 and 60 days at room temperature.
Their key move is to decompose the drift into two parts. There is a systematic component, an average leakage shared across cells, and a stochastic component that varies randomly from cell to cell and is dominated by device-to-device variability. The two demand different remedies. The systematic drift is cancelled by an adaptive read voltage, a single global reference that is retuned as the array ages, which the authors relate to the approach used in temperature-resilient neuromorphic chips. The stochastic, zero-average component cannot be nulled by any global reference because it has no shared direction. For that they use batch-normalization recalibration, an unsupervised step that re-estimates each layer's activation statistics, its means and variances, from a set of representative inputs, with no labels required, so the network re-centres itself around the perturbed weights.
The numbers show why both are needed. For one network with a 93.7 percent baseline, recalibration alone fell to 59.6 percent at 60 days, while adding the adaptive reference held it at 91.4 percent. For a harder network with an 82.1 percent baseline, recalibration alone gave 45.9 percent at 60 days against 78.3 percent with both corrections. Neither fix suffices alone; the systematic reference stops the collapse and the statistical recalibration cleans up the residue.
Where a skeptic should push
Two caveats bound the result. First, the accuracy figures are system-level simulations calibrated by experiment, not measurements from a fabricated end-to-end accelerator, and the workloads are standard image-classification benchmarks. The device retention data are genuine silicon; the recovery-to-within-a-few-points headline is a modelled consequence of that data pushed through convolutional networks. That is a reasonable methodology, but it is not the same as demonstrating a running analog accelerator that holds accuracy for two months.
Second, and more consequential for any near-tissue use, retention was characterised at room temperature. Floating-gate charge loss is a thermally activated process, so leakage accelerates with temperature; at a typical retention activation energy the rate rises several-fold between bench and body temperature, so 60 days at room temperature is closer to a couple of weeks at 37 degrees Celsius. There is a second temperature effect the paper also does not test: the cell is read in subthreshold near 1 volt, where current depends exponentially on temperature through the thermal voltage, so operating at 37 degrees perturbs read current and amplifies device mismatch during use, independent of any long-term charge loss. The most load-bearing assumption for transplanting this result to a bioelectronic context is therefore that room-temperature behaviour is representative, and for a body-temperature deployment it is not.
The steelman remains strong. The retention measurements are real, the systematic-versus-stochastic decomposition is principled, and the adaptive-reference technique has prior grounding in temperature-resilient designs. As a statement about analog in-memory compute in a benign environment, the reliability accounting is honest and useful.
Analog drift at the recording front end
The connection to microelectrode arrays is not in this paper, which never mentions biopotentials, so treat what follows as an extrapolation grounded in the paper's mechanism rather than a claim the authors make. The link is real all the same. A high-density array streaming thousands of channels at around 20 kHz produces a data torrent that dominates power and bandwidth, and the field's answer is to push processing, spatial filtering, spike detection, template matching and compression, toward the array itself. Analog in-memory computing is one credible way to do that vector-matrix arithmetic at very low power, and floating-gate cells are attractive precisely because they need no exotic process, only mature CMOS with no extra masks.
The opportunity is that this study is evidence the reliability objection to analog near-sensor compute is not fatal. Charge drift that would otherwise wreck an analog filter or classifier over weeks can be held to a few points of degradation with an adaptive reference plus periodic recalibration, giving an acquisition designer a template for keeping analog coefficients, per-channel gain trims, filter taps, detection thresholds, usable across a two-month experiment. The systematic-drift half of the fix maps reasonably onto instrumentation practice, since retuning a global read reference to null an average offset is functionally akin to the auto-zeroing or chopper-stabilised reference a good amplifier already uses, though the analogy should not be pushed too far: an auto-zeroed front end cancels per-channel input offset continuously to sub-microvolt levels, whereas the read-voltage scheme re-centres a population-level mean and needs an explicit drift estimate to set it.
Here I have to correct an argument I first reached for and then had to abandon under review, because it is instructive. I initially claimed that the second half of the fix, the statistical recalibration, has no in-situ analog for a recorder, on the reasoning that you cannot pause living tissue and push a known dataset through it. That is wrong, and I retract it. The drift being corrected lives in the electronics, not the tissue, so the electronics can be recalibrated in place by two routes the paper's own mechanism permits. Because the recalibration is unsupervised, needing only representative inputs, a recorder can re-estimate activation statistics passively from the live neural stream it already captures, with no stimulation. And an on-chip electrical self-test can inject known calibration signals, a reference current or a voltage staircase, directly into the readout chain while bypassing the electrodes, re-estimating per-channel gain, offset and noise the way a data converter is trimmed. The synthetic-signal path characterises the silicon fully. What genuinely resists in-situ correction is narrower and worth stating precisely: passive statistic tracking cannot separate weight drift in the memory from real non-stationarity in the tissue, because the live input distribution is itself moving as the culture develops and adapts; the electrode-tissue interface impedance cannot be recalibrated with synthetic electrical stimuli, since it depends on the biology; and validating the corrected output against ground truth has no in-situ form when the tissue's true state is unknown. That is the real threat, and the 37 degree environment sharpens it, because thermal acceleration grows the systematic drift the global reference cancels anyway while likely, though this is untested here, also widening the uncompensable stochastic spread that sets the usable lifetime.
The bottom line
What is established is a device fact and its system-level consequence in a benign setting: floating-gate analog weights drift measurably over 60 days at room temperature, and a two-part correction of adaptive reference plus unsupervised statistical recalibration recovers image-classification accuracy to within roughly 2 to 4 percent. What is asserted, and untested, is that this survives the transplant to a warm, chronic, near-tissue recorder. The honest reading for array hardware is that analog in-memory processing at the electrode is viable but not calibrate-once; it demands an active compensation loop. Both halves of that loop do transfer to a recording front end, one as a read-reference retune and one as passive or self-test recalibration of the electronics, which is why an earlier version of this piece was wrong to call the second half impossible in situ. The residual hazards are subtler: telling memory drift apart from genuine tissue change, recalibrating the electrode-tissue interface, and operating at 37 degrees where both retention loss and subthreshold read current worsen. What would confirm the transplant is an elevated-temperature retention and operation characterisation together with a self-calibration scheme that does not require injecting signals into the tissue. What would break it is the finding that stochastic, cell-to-cell drift at body temperature, compounded by subthreshold thermal sensitivity, swamps any reference-based correction on the timescale of a real experiment. Analog compute at the array is a genuine efficiency lever; this paper is the reminder that it comes with a maintenance contract.
Frequently asked questions
What is retention loss in a floating-gate memory?
Charge stored on the floating gate slowly leaks away, lowering the transistor threshold and raising the current it sources at a fixed read voltage. In an analog memory that current is the stored weight, so leakage directly corrupts the value rather than flipping a correctable bit.
Why does the fix need two separate corrections?
Drift splits into a systematic average shared across cells and a stochastic part that differs cell to cell. A single adaptive reference can cancel the shared component but cannot touch the random one, which is why a separate unsupervised recalibration of the activation statistics is needed to recover the last several points of accuracy.
How large was the recovery?
For a network with a 93.7 percent baseline, recalibration alone dropped to 59.6 percent at 60 days while adding the adaptive reference held 91.4 percent. For an 82.1 percent baseline network the figures were 45.9 percent versus 78.3 percent. Both corrections together land within about 2 to 4 percent of baseline.
Why does this matter for a microelectrode array?
High-density arrays generate more data than they can cheaply move, so processing is drifting toward the array itself. Analog in-memory computing can do that arithmetic at low power in mature CMOS, but its stored coefficients drift, so this reliability study bears directly on whether at-array analog compute is durable.
Can an at-array analog processor recalibrate itself in place?
For the electronics, yes. The recalibration is unsupervised, so a recorder can re-estimate statistics passively from the live neural stream, and an on-chip electrical self-test can inject known signals into the readout while bypassing the electrodes. What resists in-situ correction is the electrode-tissue interface and separating memory drift from genuine change in the tissue.
Is room-temperature retention a safe assumption for bioelectronics?
No. Floating-gate charge loss is thermally activated, so a front-end at 37 degrees Celsius drifts several times faster than the room-temperature curves indicate, and subthreshold read current is itself exponentially temperature-dependent. The paper characterises neither elevated-temperature retention nor operation, which is the condition a near-tissue recorder would actually face.
References
- Brazzini M, Filippeschi G, Catania A, Strangio S, Iannaccone G. Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing. arXiv. 2026. arXiv:2607.25058v1. Accessed 2026-07-31.