A programmable PWM built on one memristor, and what it says about stimulation channels

What the work claims

This is a primary experimental result, built and measured on a bench rather than simulated. Wu, Lei, and Liu at Penn State claim the first memristor-based PWM generator that is both programmable and fast enough for modern switching converters: measured carrier frequencies of 144.7, 159.6, 181.7, and 204.2 kHz, set purely by programming one Knowm chromium-type memristor to four different resistance states.¹ That matters because the field's previous memristor PWM work sat at 10 Hz in simulation and the authors' own earlier circuit reached only 20 kHz; power converters, especially silicon-carbide and gallium-nitride designs, switch in the tens to hundreds of kilohertz.¹

The power claim is equally specific. Generating a single PWM signal to drive a real buck converter, the memristor circuit consumes 30.36 mW; a TI F28379D DSP with everything except its EPWM1A module disabled consumes 338.38 mW for the identical function; a conventional analog PWM chip consumes 30.43 mW but cannot be programmed at all.¹ The memristor version, in other words, matches the analog circuit's power while adding programmability, and beats the digital controller by roughly 92 percent on the PWM-generation task alone. The converter outputs agree with the DSP's within about 100 mV at an 11.4 V output, so the analog signal quality is comparable, not merely cheap.¹

How it works

A PWM generator needs a carrier. The circuit builds a triangular one from a Schmitt trigger and an integrator, and the carrier frequency is set by f = R2 / (4 R1 C1 (R5 + RM1)), where RM1 is the memristor's resistance.¹ A memristor is a two-terminal device whose resistance depends on the history of applied voltage, and it keeps its state when power is removed. Programming it to a chosen resistance therefore programs the oscillator's frequency, with no register, no counter, and no clock.

The engineering is in the constraints the devices impose. Commercial memristors switch stochastically: hitting a target resistance takes a write-verify loop, and in this work the loop used 0.8 V, 50 microsecond write pulses with a 0.1 V read between pulses, accepting the result when it lands within plus or minus 10 percent of target.¹ Across nine target resistances from 7 to 75 kOhm, 50 programming trials each, every trial landed inside the window; the spread at a 21 kOhm target was a standard deviation of 946.55 Ohm, about 4.5 percent, and the number of write pulses needed varied from 2 to 11, with about 82 percent of trials converging in 3 to 9 pulses.¹ A fixed pulse count would not have worked; closed-loop verify is what makes the device usable.

Two more constraints shape the design. First, the voltage across the memristor must stay below its roughly 0.33 V threshold during normal oscillation, or the state drifts and the frequency walks; the paper derives a maximum allowable memristance of 2 Vth R2 / Vdd and adds a series resistor R5 to keep the carrier amplitude large enough for noise immunity.¹ Second, a hysteresis comparator generates the PWM output so that small disturbances on the carrier do not cause false switching.¹ The paper is candid that measured frequencies ran up to 12.62 percent below its own first-order calculation, which it attributes to parasitic capacitance in the prototype, and that the older two-memristor divider topology fails outright at these frequencies because package RC time constants, not memristor dynamics, come to dominate the waveform.¹

Where a skeptic should push

The single most load-bearing assumption is that a plus-or-minus 10 percent programming window is acceptable. Everything the paper demonstrates flows from accepting that tolerance; the 100 percent hit rate and the 4.5 percent standard deviation are conditional on it. For a converter's switching frequency, 10 percent is usually benign. The paper never tests whether the tolerance survives operating life: programming endurance, retention at temperature, and drift after millions of carrier cycles are surveyed from the literature in its discussion rather than measured here.¹

Second, the 92 percent power figure is honest but narrow. The DSP is stripped to one PWM module; the memristor board excludes its own programming hardware, which lived on an external Discovery board and takes 2 to 11 pulses per setting. The fair comparison is PWM-generation power only, not whole-system energy, and the authors say so by how they set up the measurement.¹ Third, this is open-loop PWM. No feedback control of the converter, no load transients, no closed-loop regulation is demonstrated; the buck test shows the generated waveform is clean, not that a memristive controller can stabilize a loop. Finally, the headline range improvements over prior work, an 18.41x wider memristance range and a 2.79x wider frequency bandwidth, are theoretical numbers from the design equations, not measurements.¹

What a memristive trim means for MEA stimulators

Now transpose the problem. A high-channel-count microelectrode array lives or dies by its write channel: every stimulation electrode needs a way to set pulse amplitude, timing, and polarity, and the circuits that do it, DACs, timers, charge-balancing switches, level shifters, dominate the area and power budget of the headstage. Adaptive and closed-loop protocols, which pacing organoids and demand-triggered paradigms increasingly want, need those parameters to move on controller timescales. The paper demonstrates a pattern that transfers directly: a nonvolatile analog element can hold a continuously variable timing parameter with analog-circuit power, and programmability does not have to mean a digital core per channel. Thirty milliwatts versus 338 milliwatts for one programmable timing function is the kind of arithmetic that decides whether a 256-channel stimulator is wearable or bench-bound.

The near-term transfer is trim, not control. Front ends full of analog quantities that drift and vary, transimpedance feedback values, reference currents, offset voltages, per-channel gain corrections, are exactly the parameters a memristor can hold without a DAC and without burning static power. Closing the calibration loop on-chip at power-on, the same write-verify procedure the paper uses, is a plausible architecture for per-channel analog trim on an array. That is the genuine opportunity, and it is grounded in the paper's demonstrated mechanism rather than in hope.

The genuine threat is the same mechanism read as a safety case, and here the paper's own numbers become uncomfortable. A stimulus amplitude or charge that wanders by 10 percent is not a degraded spec; it is a different dose delivered to tissue, and the paper's empirical programming distribution says plus-or-minus 10 percent is what this device class offers with a verify loop attached. Worse, the drift constraint that shaped the whole circuit, keep the voltage across the memristor below its 0.33 V threshold at all times, is precisely the constraint most likely to be violated in an array's environment: stimulation transients, stimulation artifacts, and saline-adjacent leakage all share the same pins as any trim element placed near the front end. A switching transient that crosses the threshold rewrites the trim state silently; there is no register to read back that reveals it happened. And the noise-immunity trade the authors navigate, carrier amplitude capped near twice the threshold voltage, below 0.66 V in this design, is the same small-signal wall that governs any analog function sitting microvolts away from a biological interface: programmability bought in the analog domain is paid for in noise margin.

The non-obvious implication is a partitioning rule. The paper hands array designers a clean line: parameters biology tolerates loosely, burst cadence, refresh intervals, non-critical biases, front-end offsets that can be re-verified against a known signal, are candidates for memristive trim with real power savings. Parameters where error is a dose, stimulation charge, pulse amplitude, anything the tissue integrates, stay in the verified digital domain, or at minimum behind a mechanism that re-verifies delivered charge against an independent reference every time it changes. The 2-to-11-pulse programming loop, seconds at best on external hardware, also quietly rules out fast dynamic reconfiguration: a parameter that must move within a biological inter-spike interval cannot be a memristive one. The hype-correction is symmetrical: this is not a memristive stimulator around the corner, and it is also not a curiosity; it is a trim technology with a well-characterized error budget, which is more than most analog programmability schemes offer.

The bottom line

Established by measurement: a commercial memristor can serve as the programmable timing element of a PWM generator operating at 144.7 to 204.2 kHz, programmed repeatably within plus or minus 10 percent by closed-loop write-verify, and generating converter-grade waveforms at about one tenth the PWM-task power of a DSP. Hypothesis, not shown: retention and endurance over operating life, closed-loop regulation, and any behavior at foundry-integrated rather than packaged-device scale. The application to microelectrode arrays is my reading, not the authors'. What would settle the array case is a trimmed front end whose delivered stimulus charge is re-verified against an independent reference after programming and after prolonged stimulation, with the trim drift measured, not assumed, across the artifact environment of a real array. Until then, trim boldly, stimulate conservatively.