Scaling analog silicon by shipping spikes unreliably on purpose

What the work claims

This is a computer architecture design paper, validated in simulation and marked with a 2026 IEEE copyright notice, not yet backed by silicon. Heinemann and Schemmel claim that a single interconnection network can carry the two incompatible kinds of traffic a scaled analog neuromorphic system produces: event messages, where only timing matters and a small loss rate is acceptable, and non-event messages, configuration data and processor traffic, where a single corruption is fatal.¹ The design multiplexes both over one wide parallel die-to-die link running at 22 Gbit/s per direction per port, built from about eleven 2 Gbit/s links each tested to a bit error rate at or below 1e-10.¹ Events get a 19-bit address payload and no error control at all: the arrival time on the receiving chip is the presynaptic time. Non-event traffic travels in 90-bit flits with a 7-bit CRC, is retransmitted on error under an ARQ protocol, and is paced by credit-based flow control, with dimension-ordered routing that preserves message order.¹ Simulation of the synthesizable implementation reports 95 percent link utilization across a wide range of spike-to-secured traffic mixes at 1e-10 bit error rate, event round-trip latency of 32 ns between two routing chiplets, and a total router plus protocol area of about 0.17 mm-squared in 65 nm, of which 0.13 mm-squared is buffers.¹

How it works

The motivation is physical. Each BrainScaleS-2 chip pairs an analog core that does not benefit from newer process nodes with digital logic that does, so the authors split the system across chiplets and connect them in a 2D mesh through dedicated routing dies.¹ Because the analog neurons run continuously and cannot be paused, a scaled system is globally asynchronous, and congestion on any link will jitter or drop spike timing. The design accepts this rather than fighting it. On each 22-bit physical transfer every 1 ns, one bit marks the payload type; a weighted arbiter prioritizes event traffic while guaranteeing a configurable minimum bandwidth to secured traffic, so the link is partitioned dynamically instead of statically.¹ Type and framing bits are protected with a Hamming code whose pair encoding costs only 6 bits for two consecutive events and 7 bits otherwise, since a misread type bit would corrupt a whole transfer in a way a payload CRC cannot catch.¹

The event payload uses address-event representation: 19 bits label up to 524,288 neurons, enough for at least 1,024 BrainScaleS-2 chips, and the paper notes real systems would need fewer unique labels because each chip only sees events from a subset of neurons.¹ Events are transmitted without checksums and without retransmission; congestion drops them, on the argument, drawn from biology, that spiking networks tolerate unreliable synaptic delivery.¹ Everything else gets the conservative treatment: 90-bit flits with a CRC giving Hamming distance 3, cumulative acknowledgements piggybacked on flits that also carry flow-control credits, retransmission triggered by negative acknowledgement or timeout, and wormhole routing over a fixed X-Y path so ordering is preserved and no reorder buffer is needed.¹ The whole protocol was written in synthesizable SystemVerilog and Amaranth, formally verified, and compiled to a cycle-accurate model coupled to simulated lossy links.¹

The evaluation is honest in both directions. For the surrogate-gradient training workload, hardware-in-the-loop learning where on-chip ADCs stream membrane traces to a host, the network sustains 95 percent link bandwidth across traffic mixes at 1e-10 bit error rate, with error-recovery behavior extrapolated from 200 injected bitflips.¹ But the authors also report that a 16 by 16 mesh contains 960 chip-to-chip links, and that their mean-time-between-failure model scales down to order-of-minutes for the full system in the worst case, with the caveat that failing to sustain bandwidth is usually tolerable for ADC samples.¹ Their comparison table puts the design at 22 transmitted bits per event against 20 for the existing BrainScaleS-2 FPGA link, 29 for an EXTOLL-based network, 40 or 72 for SpiNNaker, 32 or 64 for spiNNlink, and 24 for DYNAP-SE2.¹

Where a skeptic should push

The most load-bearing assumption is that dropped spikes are harmless. That is defensible for feed-forward spiking networks emulated on BrainScaleS-2, but it is imported from biology, not proven for every workload: recurrent dynamics, precisely timed spike trains, and any closed loop that stimulates based on detected events are all places where a congestion-dependent loss process is a systematic bias, not noise. Demonstrated versus asserted: it is demonstrated, in simulation with formally verified RTL, that the link meets its latency and bandwidth targets for the chosen workloads; it is asserted that a deployed mesh behaves the same, and the event router that would actually matter in deployment is explicitly out of scope, with a simple broadcast router standing in for evaluation.¹

Second, the reliability numbers are extrapolations. The 1e-10 bit error rate is a tested property of the physical links, but per-link mean-time-between-failure is computed, not measured, from recovery times after 200 injected bitflips, and realistic error rates are too low to simulate directly.¹ The order-of-minutes worst case for a 16 by 16 mesh is the authors' own number, and it means the architecture as specified needs an operational story, degraded-mode experiments, checkpointing, at exactly the scale it is designed for. Third, the speed of light: at 1,000 times biological acceleration, 32 ns of round-trip jitter is 32 microseconds of emulated time, comfortable for most plasticity rules; anyone porting this link discipline to real-time systems inherits the nanosecond numbers without the acceleration divisor. And the area figure excludes I/O cells, which on a die whose whole job is driving parallel die-to-die links is not a rounding error.¹

Two-class traffic and the array backplane

The non-obvious implication for microelectrode array instrumentation is that this paper draws the partition every large array system needs but few publish: which of your data may be lost, and which must never be. A CMOS microelectrode array headstage or multi-tile acquisition backplane carries exactly the same two classes as the BrainScaleS mesh: spike event streams and derived features, which are redundant across channels and tolerant to occasional loss, and configuration, calibration, impedance telemetry, and stimulation-arming data, where a flipped bit is a misfired stimulus or a corrupted calibration. The authors' mechanism, dynamic weighted arbitration with a guaranteed minimum secured bandwidth on a shared link, is directly portable: it avoids the classic failure of statically partitioned links, which strand bandwidth when spike traffic is low and starve telemetry when it bursts.¹ The 22-bit-per-event accounting is a useful budgeting discipline too; it says a link's true cost is bits per event under real header overhead, and their comparison table is a reminder that published event-link numbers are rarely comparable without normalizing that way.¹

The threat is just as transferable. The design's cheapest trick, unsecured, timestamp-by-arrival event delivery with deliberate drops under congestion, is safe only because a missing spike perturbs an emulation statistically. In a closed-loop MEA system that stimulates in response to detected events, a congestion-dependent loss process in the feedback path is a phase error and a stability hazard, and the same link would need the secured traffic class where the neuromorphic designer skimped. The scaling arithmetic is the second export: with 960 links, worst-case mean time between bandwidth failures collapses to minutes, which is the same arithmetic that will govern wafer-scale and tiled CMOS arrays with thousands of serial links, and the authors' recovery-time-based failure model, rather than naive per-link rates, is the right way to budget it.¹ The opportunity, meanwhile, is the chiplet partition itself: the argument that analog front-ends do not benefit from advanced nodes while digital routing does maps one-to-one onto separating an electrode-interface die from a routing and aggregation die, letting each be built in the process that suits it. An array backplane designed with this paper's traffic classes, its per-event bit budget, and its unsparing failure arithmetic would be more honest, and more reliable, than most of what the field wires up today.

The bottom line

Established, within a simulation-only study: a single die-to-die link can carry droppable, unsecured spike events and CRC-protected, retransmitted configuration traffic together at 95 percent utilization, with 16 ns single-hop event latency and modest area, and the traffic-class split is formally verified RTL, not a sketch.¹ Not established: silicon behavior, multicast event routing, and system-level reliability beyond the authors' own worst-case estimate of minutes between bandwidth failures at mesh scale.¹ The design is confirmed when a taped-out routing chiplet meets these numbers on real links; it is broken if dropped or jittered spikes turn out to corrupt workloads beyond the feed-forward tolerance the argument rests on. For array instrumentation the paper's value does not depend on BrainScaleS succeeding at all: it is a published, quantified template for partitioning an acquisition backplane into data that may be lost and data that must not be, and for doing the link-count reliability arithmetic before the link count chooses itself.