Volatile memristor calibration, from I-V sweep to SPICE neuron

What the work claims

Endres, Töpfer, Blum, Honig, and Schaaf present a primary experimental result plus its modelling consequences: a fabricated lateral Pt/TiO2/Ag volatile memristor is characterized on a Keithley 2450 source-measure unit, the measured current-voltage and pulse data are fitted to a compact memristor model extended with a leakage term, the fitted model is implemented as a reusable SPICE subcircuit, and that subcircuit is validated against the measurements and demonstrated inside a leaky integrate-and-fire (LIF) neuron circuit, where the memristor replaces the threshold transistor¹. The claim is methodological as much as technical: a volatile device with seconds-scale relaxation, which fails every non-volatile memory benchmark, is exactly the right element for a spiking threshold, and there is a reproducible five-stage pipeline for proving that.

How it works

The device is a two-terminal lateral structure with platinum and silver electrodes around a TiO2 switching layer. All characterization was run at a 1 microamp compliance current to protect the dielectric. A triangular sweep from 0 V to 6 V, down to -6 V, and back (1.2 minutes total) produced the pinched hysteresis loop that confirms memristive behaviour, with resistance moving between about 4 MΩ and 80 MΩ. Pulse measurements used a 10 V, 1.0 second SET pulse followed by a 0.2 V, 15 second READ pulse, repeated cyclically; the device switches to roughly 3.3 MΩ on the SET phase and then relaxes back to 40 to 100 MΩ during the READ phase, with visible cycle-to-cycle variation¹.

Two measurement artifacts matter for anyone reading device papers. First, once the current hits the compliance limit, the source-measure unit's control loop caps the applied voltage between 3.3 V and 3.8 V, and the recorded I-V curve from that point on reflects the instrument, not the device: horizontal segments and fluctuating apparent resistance. The authors excluded compliance-limited points from the fitting dataset rather than pretending their model explains them. Second, the paper's own 0.1 second sampling interval is eight orders of magnitude slower than the roughly 1 nanosecond switching transients reported in the fast-switching literature, so the fitted dynamics describe the envelope, not the transition¹.

The model is the Yakopcic generalized memristor: a hyperbolic-sine current-voltage relation with different coefficients for the two polarities, an exponential threshold function with Vp = 1.5 V and Vn = 1.0 V, the Biolek window function to bound the internal state, and a new leakage term l(x) = -(x - xeq)/τ that drives the state back toward equilibrium when the bias is removed. Parameters were optimized by coordinate descent on the normalized mean squared error between simulated and measured curves. Fitting the relaxation tail of the pulse data with the equilibrium state set to zero gives a mean time constant of about 4.2 seconds, using the measured 3 MΩ value at the start of the 15 second read interval and 108 MΩ at the end. Notably, the fitted negative-threshold coefficient An came out negative, reflecting that this device decreases its memristance under negative bias, which the authors flag as unlike most published fits¹.

The SPICE implementation is two behavioural current sources and a 1 farad integrating capacitor: one source models the I-V relation, the other integrates the state equation, so the internal state lives as a pseudo-voltage. In the demonstration application, the memristor replaces the MOSFET threshold element in a published floating-body LIF neuron design; driven by 70 microamp current pulses with a 28 ms period and 17 ms on-time, the circuit produces repeated output spikes of up to roughly 80 microvolts, with the leakage term resetting the device after each spike so it can fire again. Without the leakage term the device would latch in its low-resistance state and fire once¹.

Where a skeptic should push

The load-bearing assumption is that a deterministic compact model fitted to one device is a sound basis for circuit design. The paper's own validation data argue both ways. Below the compliance limit, simulation and measurement agree well; in the compliance region and during relaxation, the measured traces show fluctuations that the deterministic model does not reproduce, and the authors attribute them honestly to stochastic device behaviour. They also note metastable intermediate resistance states in the relaxation data that the single-exponential leakage term misses. So the model is good enough to demonstrate a neuron and not good enough to predict the noise that would dominate any real signal chain built on this device¹.

Sample size is one device, and the authors say future work needs measurements on a larger number of devices to capture device-to-device and cycle-to-cycle variability. The ON/OFF ratio of about 35 under pulsed excitation falls short of the 50 cited as a memory benchmark and far short of the 500 wanted for analog computing, though the high Rmax above 100 MΩ does meet the high-resistance analog benchmark, and the seconds-scale decay is acceptable for synaptic-style operation. The volatility itself is a compliance-current artifact as much as a materials choice: the cited literature shows that 1 to 10 microamp compliance gives volatile switching relaxing in seconds, while 500 microamp to 1 mA forms robust non-volatile filaments. Change the compliance and you change the device class¹.

Finally, the neuron demonstration is a simulation of a circuit, not silicon. The 80 microvolt output spike amplitude is a small number with a large consequence: any physical realization needs an amplifier almost immediately, so the memristor has not removed the analog front end, it has just moved it one stage later.

Calibrated compact models and the at-array neuron

For microelectrode array hardware the interesting object here is not the TiO2 device, it is the pipeline: measure with an instrument whose artifacts you can name, fit a model only to the data you trust, implement it in a standard simulator, and validate end to end in the target circuit. That is precisely the discipline an array lab would need before trusting any per-electrode active element, whether a volatile memristor used as an adaptive threshold, an at-array LIF encoder, or a tunable impedance element at the tissue interface. The field currently evaluates such elements from datasheets and idealized simulations; this paper is a template for evaluating them the way an instrumentation engineer should, from measured data with the instrument's fingerprints removed¹.

The non-obvious implication is about what volatility is for. A relaxation time constant of about 4.2 seconds sounds like a retention failure, and by memory benchmarks it is. But seconds-scale memory is exactly the integration window of slow biological phenomena: synaptic depression, burst envelopes, metabolic drift, glial signalling. A volatile threshold element at the electrode does the temporal averaging that would otherwise cost a digitizer, an integrator, and the power to run both, and then forgets on its own. The same physics that disqualifies the device as storage qualifies it as a temporal filter matched to the tissue. That reframe is the real transferable idea: stop benchmarking at-array neuromorphic elements against non-volatile memory targets and start benchmarking them against the time constants of the signals they are meant to condition¹.

The threat is overconfidence in deterministic models. Every number above, from the 4.2 second time constant to the fitted thresholds, comes from a single device smoothed by low-pass filtering, and the paper itself shows the residual stochasticity is the part that matters for signal integrity. An array embedding hundreds of these elements would see the distribution of that stochasticity, not its mean. Designing the acquisition chain against the fitted model alone would systematically underestimate the noise floor of the at-array compute layer, which is the one layer you cannot post-process your way out of because the corruption happens before digitization. The compliance-current lesson generalizes uncomfortably well: whenever an active element in the chain saturates, what the recorder logs afterward is the recorder, and models trained on that log inherit the lie.

There is also a quieter opportunity in the failure modes the authors surfaced. The negative fitted coefficient and the metastable intermediate states are device physics trying to get out of the chosen model class; an array with hundreds of nominally identical elements, each characterized by the same five-stage pipeline, would be an excellent instrument for mapping that physics statistically. In that sense the MEA community does not just need this workflow, it is positioned to extend it at a scale a single-device device-physics lab cannot.

The bottom line

Established: a measured volatile TiO2 memristor can be carried from characterization through parameter fitting to a validated SPICE model that demonstrably supports a leaky integrate-and-fire neuron circuit, with a mean relaxation constant near 4.2 seconds. Hypothesis, still open: that the fitted deterministic model survives contact with device-to-device variability and cycle-to-cycle stochasticity once more than one device is measured. What would confirm it is a multi-device study reporting the distribution of the fitted parameters and the residual noise; what would break it is evidence that the metastable intermediate states, not the exponential leakage, dominate the relaxation in most devices. For MEA hardware, the durable takeaway is the calibration discipline and the reframing of volatility as a matched temporal filter, not the specific device.